1. Field of the Invention
The present invention relates to a computer system, a method of detecting a stall (e.g., a non idle state which continues for more than a predetermined period of time) in a computer system, and a signal-bearing medium embodying a program causing a computer system to perform a method of detecting a stall in a computer system, and in particular, it relates to a computer system and a system monitor program, which allows the system to stably operate without suffering from adverse effect due to fault of an input/output bus.
2. Conventional Art
Heretofore, a computer system has included a large number of processors and input/output buses (e.g., PCIs (Peripheral Component Interconnects)) which are connected for one system such as a multi processor system including 16 to 32 processors, and a multi-processor system having input/output bus slots (e.g., PCI bus slots) including more than 64 processors.
Such a computer system, in general, has been often used for an application (i.e., a mission critical application) which is required to be highly reliable and fault-tolerant. Consequently, high availability is required. Hence, a technology relating to fault detection and its processing such as capable of minimizing the effect of an error has been required.
Japanese Patent Laid-Open No. 2002-215557 discloses detection of a phenomenon (totally different from a “stall” referred to by the present invention) in which a plurality of target devices reply to the detection of an error in the PCI bus, in particular, one of the PCI cycles.